One important stage in the manufacture of semiconductor devices is the formation of isolation areas to electrically separate the active devices or portions thereof, that are closely integrated in the silicon wafer. The particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Unintended current should not flow between source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process, movement of dopant atoms, for example, of boron, phosphorus, arsenic, or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and those dopant atoms within the silicon wafer.
It is typically employed when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as "trench isolation" has been used to limit such flow. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same or different polarity type (i.e., p-type versus n-type). The trench regions are formed in the semiconductor substrate by recessing the substrate deep enough for isolation and refilling with insulating material to provide the isolation among active devices or different well regions.
In a conventional process, a significant problem with STI is that isolation oxide is exposed to numerous etch and clean sequences during subsequent processing, leading to recessing of the trench oxide. Excessive trench oxide loss may lead to inverse narrow width effects, excessive topography, and photo-alignment problems, excessive leakage on trench sidewalls and isolation breakdown. Consequently, device quality and reliability may be impaired.
Refer to FIG. 1. A cross-section of an STI structure 100 is built with a prior art process. The shallow trenches 120 in the silicon substrate 110 have received a fill oxide 130. However, subsequent processing of the structure 100 has contributed to oxide recessing 140. Oxide recessing 140 degrades the performance of the transistor active area 150.
Accordingly, a need exists for a shallow trench isolation process that lessens the loss of trench oxide as the process technology approaches fractional microns.